Altera Corporation was an American manufacturer of programmable logic devices (PLDs), reconfigurable complex digital circuits. The company released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs, Quartus II design software, and Enpirion PowerSoC DC-DC power solutions.

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Altera

Category: Content
Type: Blog Article

Generated 4 days ago

Altera

Category: Content
Type: Youtube Video

Generated 4 days ago

Altera

Category: Content
Type: Youtube Video

Generated 4 days ago

New videos detected

  • Meeting FPGA Requirements with Enpirion® Power Solutions

    Start your FPGA power design the right way by maximizing your system performance, while meeting the most stringent power, budget, and solution size requirements needed for an FPGA with the EM2130. Learn more about Enpirion Power solutions: http://bit.ly/2numSLJ Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Youtube Video

Generated 4 days ago

New videos detected

  • Getting Started with EM2130

    Get an overview of how easy it is to power any programming logic device with the EM2130 Eval kit’s default configuration. Learn more about Enpirion Power solutions: http://bit.ly/2numSLJ Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Youtube Video

Generated 4 days ago

New videos detected

  • Creating Custom Configurations on the EM21xx PowerSoCs to suit any application

    Using the Intel Enpirion Digital Power Configurator GUI, learn how to generate a custom configuration and a programming file with a simple example. Learn more about Enpirion Power solutions: http://bit.ly/2numSLJ Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Blog Article

Generated 1 week ago

Altera

Category: Content
Type: Youtube Video

Generated 1 week ago

New videos detected

  • Switching the CDR reference clock source on Arria 10 FPGAs

    This video will show the users how to perform dynamic reconfiguration to switch the CDR refclks with the embedded streamer and multiple reconfiguration profiles in an Arria 10 device. Dynamic CDR refclk switching enables the transceiver RX channel to support different data rates without the need to re-program the device. This video will cover the IP required, IP configuration and a Modelsim simula...

Altera

Category: Content
Type: Blog Article

Generated 2 weeks ago

Altera

Category: Content
Type: Youtube Video

Generated 2 weeks ago

New videos detected

  • 如何在 Arria 10 中实现 IO 锁相环 (PLL) 重配置

    This video shows you how to implement IOPLL reconfiguration in an Arria 10 FPGA. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • 如何在 Arria 10 中实现 IO 锁相环 (PLL) 动态相移

    This video shows you how to implement the IOPLL dynamic phase shift feature in an Arria 10 FPGA. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • 创建 UEFI LCD 应用程序、运行 LCD 应用程序(第二部分)

    The Altera Arria 10 SoC UEFI Bootloader "make app" feature is enabled in the UEFI Shell i.e. after the post DDR boot stage, known as UEFI DXE Phase. It is one of the extended UEFI functionality which allows user to access to a broad range of pre-existing UEFI utility already developed by the open source community. Prior to booting the DXE phase, it will requires DDR SDRAM to be ready. Part 2 of 2...

  • 创建 UEFI LCD 应用程序、运行 LCD 应用程序(第一部分)

    The Altera Arria 10 SoC UEFI Bootloader "make app" feature is enabled in the UEFI Shell i.e. after the post DDR boot stage, known as UEFI DXE Phase. It is one of the extended UEFI functionality which allows user to access to a broad range of pre-existing UEFI utility already developed by the open source community. Prior to booting the DXE phase, it will requires DDR SDRAM to be ready. Part 1 of 2 ...

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New videos detected

  • Reading the DFE tap values in Arria10 Native PHY

    This video will show the user how to read the converged DFE tap values in the Arria 10 Native PHY using system console. DFE compensates for inter-symbol interference (ISI). It can help to improve the RX signal integrity performance in a transceiver link. In adaptive mode, the DFE tap values are controlled by the Adaptive Parametric Tuning Engine and will converge to specific values. This video wil...

  • Constraining the IOPLL location for LVDS SERDES in Arria 10 devices

    This video shows users how to manually constrain the IOPLL location for the LVDS SERDES in Arria 10 devices. This enables the user to select the specific IOPLL for an LVDS channel in design. This video will demonstrate the steps to locate the IOPLL location in Chip Planner and then use the Assignment Editor to constrain the location. This video will also cover Altera LVDS SERDES IP configuration f...

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New videos detected

  • External Memory Interface Device Selector Tutorial

    This is a tutorial and introduction of the External Memory Interface Device Selector. It will walk you through some background information on the tool as well as talk about the usefulness of the different parts of the tool. The tutorial will show you the Device Selector GUI and a walkthrough of the Bandwidth Tool. A link to the wiki and a download of a copy of the tool is located here: http://www...

  • System Console - Part 3

    This video describes the system console tool from Intel PSG. This product allows a user to peek into the register map of an FPGA design using a text or graphical interface. This video shows demonstrations and links to help you understand use of this tool.

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New videos detected

  • Chip to Chip link tuning Transceiver Toolkit

    This video describes how to setup two FPGAs to perform chip to chip link tuning.

  • External Memory Interface Specification Estimator

    This video describes the EMIF specification estimator. See a demonstration of how this tool works. This video shows the value of seeing how core speed, data width, use of soft/hard controller, depth expansion, and memory topology can effect max clock rate and data rate support on all of device families.

  • Blueprint Reference Design Part 1

    Create a quick system to validate your pinout using BluePrint Instructional Video - Brief introduction to BluePrint and the flow - Talk about the need to have a synthesizable design that has all the required I/O for rules checking - Use Qsys to show how quickly a system can be created. - Walk the user through an Arria 10 system that contains 8 DDR4x16s and 48 transceivers. - Show the use empty par...

  • Blueprint Reference Design Part 2

    Create a quick system to validate your pinout using BluePrint Instructional Video - Brief introduction to BluePrint and the flow - Talk about the need to have a synthesizable design that has all the required I/O for rules checking - Use Qsys to show how quickly a system can be created. - Walk the user through an Arria 10 system that contains 8 DDR4x16s and 48 transceivers. - Show the use empty par...

  • System Console - Part 2

    This video describes the system console tool from Intel PSG. This product allows a user to peer into the register map of an FPGA design using a text or graphical interface. This video shows demonstrations and links to help you understand use of this tool.

  • System Console - Part 1

    This video describes the system console tool from Intel PSG. This product allows a user to peer into the register map of an FPGA design using a text or graphical interface. This video shows demonstrations and links to help you understand use of this tool.

  • Simple power sequencing using MAX 10 FPGAs

    This video will include a design example file on how to design simple power up sequence by using a MAX 10 FPGA. The design example will help customer to speed up the design for Group 1 to 3 power up sequence for FPGAs. This video also show the advantages of using MAX10 FPGA as power up sequence device instead of using commercial available power up sequence integrated circuits.

  • How to simulate Cyclone V 8b10b IP byte ordering

    - This video will show the users how to perform manual word alignment and byte ordering in the Cyclone V Native PHY with 8b10b and double-width PCS mode. A similar method is applicable to all V series devices. With double-width PCS mode and byte SERDES enabled, the transceiver will achieve a higher data rate. Byte ordering helps to restore the proper byte order of the byte-deserialized data before...

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New videos detected

  • Nios II 以太网设计的调试技术 Part 2

    This is the second part of a video that introduces several debug techniques for Nios II Ethernet Design. They can be applied during migration of the Nios II Ethernet Design to different boards or devices. The document “Using the NicheStack TCP/IP Stack – Nios II Edition” can be downloaded from this link: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/tt/tt_nios2_tcpip.p...

  • Nios II 以太网设计的调试技术 Part 1

    This is the first part of a video that introduces several debug techniques for Nios II Ethernet Design. They can be applied during migration of the Nios II Ethernet Design to different boards or devices. Get the Nios II Ethernet Design examples from the links below. • Cyclone III and Stratix IV Ethernet Design Example can be obtained from this link: https://www.altera.com/support/support-resources...

  • Arria 10 早期功耗估算器

    This video will demonstrate to users on how Quartus software could be used to generate the .csv file for power estimation and import the files generated to the PowerPlay Early Power Estimation tool available in Altera.com in order to come out with a result of estimated power for the user as a reference while selecting the power regulators for their design. Follow Intel FPGA to see how we’re progra...

  • 使用片内调试 Nios 软核处理器

    This video describes using one of the Arria 10 External Memory Interface IP features which is the Soft NIOS Processor for On-Chip Debug. This video provides an explanation on what this feature is, example usage, descriptions of files used and steps to run the example software. This video is useful for verification engineer or design engineers debugging this interface. Follow Intel FPGA to see how ...

  • 如何在 Altera PHYLite IP 中创建已校准终端 IO

    Altera PHYLite IP supports different I/O standards and termination on input and output buffers. This can be configured through the PHYLite IP Parameter Editor. When the user selects calibrated termination values on the I/O buffer, the user is required to connect the RZQ pin from OCT Block to an external resistor. However, the On-Chip-Termination (OCT) block is not created during the PHYLite IP ...

  • JTAG 链调试程序工具

    This video describes the chain debugger tool which tests the integrity of the JTAG chain. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • How to put MAX 10 device in sleep mode

    The video will show how to use the MAX10 Power Management Controller(PMC) design for power saving in sleep mode.

  • Arria 10 Smart Voltage ID

    This video describes how to use the Arria 10 smart Voltage ID feature to reduce power in your FPGA design.

  • Using the Arria 10 Unique Chip ID feature

    Altera Unique Chip ID core allows you to uniquely identify the target FPGA. This protects your device from receiving unauthorized programming data. With this video engineers will know what is chip ID ,why to use it, and how to generate the chip ID IP block for Arria 10 devices.

  • How to setup RTL simulations in Quartus, Qsys and third party simulators

    This video describes how to setup an RTL based simulation using the IP setup simulation utility.

  • 如何生成器件的后配置 BSDL 文件

    This how-to video will show the user how to generate the post-configuration BSDL file by using Quartus II PIN file and a TCL script. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • 高级 IO 时序

    This video will show you how to estimate the signal integrity metric of single-ended output with Advanced IO Timing (AIOT) in Arria 10 devices. The AIOT allows users to estimate the signal integrity performance of a single-ended output for a specific board setup by using Quartus software only. This is helpful to find the estimated optimal IO settings without the need of third party signal integrit...

  • How To Use In-System Memory Content Editor

    This video describes the Quartus In-System Memory Content Editor feature. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • Arria 10 单工发送器和接收器

    This video will show the user how to configure the Arria 10 Native PHY simplex transmitter and receiver with dynamic reconfiguration to allow placement in the same physical transceiver channel. By default, if the dynamic reconfiguration is enabled for simplex transmitter and receiver, Quartus will not allow them to be placed into the same physical channel location. This video will demonstrate the ...

  • Max10 ADC IP 可配置采样率、Dual ADC 工具包和逻辑仿真

    This video introduces the Max 10 ADC IP configurable sampling rate feature, logic simulation and dual ADC toolkit. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Positioning & Presence
Type: Page Metadata Change

Generated 1 month ago

New page title detected.

  • New: Blog - Altera - Gestão e Marketing em Saúde
  • Old: Blog - Altera - Centro de Inteligência em Serviços

Altera

Category: Content
Type: SlideShare Presentation

Generated 1 month ago

Slide Share presentations detected

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 2 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Positioning & Presence
Type: Page Design Update

Generated 4 months ago

Altera

Category: Content
Type: Youtube Video

Generated 6 months ago

New videos detected

  • Smart Factory for Industry 4.0 with Deterministic Ethernet (802.1 TSN)

    Last year, we have seen a rapid acceleration in the definition of new standards that are the basis of the Industry 4.0 program and the design of Smart Factory of the future. New standards such as OPC-UA Pub / Sub and TSN are growing and they are used to connect the different nodes of the factory and at the same time to assure factory interface to the Cloud. Watch this demo to learn more.

  • 5G Massive MIMO Beamforming

    Massive MIMO and 3D beamforming offer a significant increase in spectral efficiency. This demonstration shows how Intel® Xeon™ processors, Intel FPGAs, and a Fortville NIC can be used to build a complete 5G solution. Huge throughput and low latency is enabled with a 100MHz carrier bandwidth, 0.2ms TTI and 64 element antenna array.

  • Intel SoC FPGA-Based Open-Source Drone Platform and Sensing Modules

    This demo showcases the Aerotenna μ series microwave radars based on Intel® Altera SoC technology, the first radars for commercial and consumer drones to utilize microwave sensing, which was previously used only on military UAVs. μLanding™ is the first and most compact microwave altimeter for drones and small UAVs, while μSharp™ is the first 360° active sense-and-avoid radar for drones and small U...

  • CNN and GZIP implementation on FPGA by OpenCL

    Convolutional Neural Network (CNN) is a Deep Learning algorithm used for various object classification. This AlexNet demo showcases the performance-per-watt advantage on a discrete Arria 10 FPGA for an ImageNet scoring application. We are also showing a GZIP demonstration which compresses data at a high throughput and compression ratio. Both of these demos have been implemented in OpenCL, which en...

  • PCIe Avalon Memory Master DMA Reference Design in Arria 10 part1

    In this 2 part video, the user will learn how to setup the hardware and run the PCIe AVMM DMA reference design in Arria 10 devices for both the Linux and Windows Operating System. Part 2: https://youtu.be/lWcjItN4byU

  • PCIe Avalon Memory Master DMA Reference Design in Arria 10 part2

    In this 2 part video, the user will learn how to setup the hardware and run the PCIe AVMM DMA reference design in Arria 10 devices for both the Linux and Windows Operating System. Part 1: https://youtu.be/CGs2Q3028ss

  • UEFI Bootloader Customization

    This video describes how to customize the UEFI bootloader configuration settings through modification of the description file: (Arria10SocPkg.dsc).

  • In System Memory Content Editor

    This video describes the Quartus In-System Memory Content Editor feature.

  • MAX10 External Memory Interface Design Guidelines

    This video provides guidelines for designing External Memory Interfaces in MAX 10 including board design.

  • Using the Soft NIOS processor to debug Arria 10 External Memory Interfaces

    This video describes using one of the Arria 10 External Memory Interface IP features which is the Soft NIOS Processor for On-Chip Debug. This video provides an explanation on what this feature is, example usage, descriptions of files used and steps to run the example software. This video is useful for verification engineer or design engineers debugging this interface.

  • UEFI HwLib Porting Part2

    For users who are familiar with Hwlib code but want to develop UEFI driver or application code, here is the guideline on how to convert Hwlib code to UEFI. Part 1: https://youtu.be/7X-98v8nKfA

  • UEFI HwLib Porting Part1

    For users who are familiar with Hwlib code but want to develop UEFI driver or application code, here is the guideline on how to convert Hwlib code to UEFI. Part 2: https://youtu.be/ZvqBzlxPAqg

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