Last year, we have seen a rapid acceleration in the definition of new standards that are the basis of the Industry 4.0 program and the design of Smart Factory of the future. New standards such as OPC-UA Pub / Sub and TSN are growing and they are used to connect the different nodes of the factory and at the same time to assure factory interface to the Cloud. Watch this demo to learn more.
Massive MIMO and 3D beamforming offer a significant increase in spectral efficiency. This demonstration shows how Intel® Xeon™ processors, Intel FPGAs, and a Fortville NIC can be used to build a complete 5G solution. Huge throughput and low latency is enabled with a 100MHz carrier bandwidth, 0.2ms TTI and 64 element antenna array.
This demo showcases the Aerotenna μ series microwave radars based on Intel® Altera SoC technology, the first radars for commercial and consumer drones to utilize microwave sensing, which was previously used only on military UAVs. μLanding™ is the first and most compact microwave altimeter for drones and small UAVs, while μSharp™ is the first 360° active sense-and-avoid radar for drones and small U...
Convolutional Neural Network (CNN) is a Deep Learning algorithm used for various object classification. This AlexNet demo showcases the performance-per-watt advantage on a discrete Arria 10 FPGA for an ImageNet scoring application. We are also showing a GZIP demonstration which compresses data at a high throughput and compression ratio. Both of these demos have been implemented in OpenCL, which en...
In this 2 part video, the user will learn how to setup the hardware and run the PCIe AVMM DMA reference design in Arria 10 devices for both the Linux and Windows Operating System. Part 2: https://youtu.be/lWcjItN4byU
In this 2 part video, the user will learn how to setup the hardware and run the PCIe AVMM DMA reference design in Arria 10 devices for both the Linux and Windows Operating System. Part 1: https://youtu.be/CGs2Q3028ss
This video describes how to customize the UEFI bootloader configuration settings through modification of the description file: (Arria10SocPkg.dsc).
This video describes the Quartus In-System Memory Content Editor feature.
This video provides guidelines for designing External Memory Interfaces in MAX 10 including board design.
This video describes using one of the Arria 10 External Memory Interface IP features which is the Soft NIOS Processor for On-Chip Debug. This video provides an explanation on what this feature is, example usage, descriptions of files used and steps to run the example software. This video is useful for verification engineer or design engineers debugging this interface.
For users who are familiar with Hwlib code but want to develop UEFI driver or application code, here is the guideline on how to convert Hwlib code to UEFI. Part 1: https://youtu.be/7X-98v8nKfA
For users who are familiar with Hwlib code but want to develop UEFI driver or application code, here is the guideline on how to convert Hwlib code to UEFI. Part 2: https://youtu.be/ZvqBzlxPAqg